含有無(wú)關(guān)項(xiàng)的序列檢測(cè)

題目描述
請(qǐng)編寫一個(gè)序列檢測(cè)模塊，檢測(cè)輸入信號(hào)a是否滿足011XXX110序列（長(zhǎng)度為9位數(shù)據(jù)，前三位是011，后三位是110，中間三位不做要求），當(dāng)信號(hào)滿足該序列，給出指示信號(hào)match。

程序的接口信號(hào)圖如下：

程序的功能時(shí)序圖如下：

`timescale 1ns/1ns module sequence_detect(input clk,input rst_n,input a,output reg match);parameter idle = 8'b00000001;parameter state1 = 8'b00000010;parameter state2 = 8'b00000100;parameter state3 = 8'b00001000;parameter state4 = 8'b00010000;parameter state5 = 8'b00100000;parameter state6 = 8'b01000000;parameter state7 = 8'b10000000;reg [0:7] c_state,n_state;reg [0:1] cnt;always@(posedge clk or negedge rst_n)beginif(!rst_n)c_state <= idle;elsec_state <= n_state;endalways@(*)begincase(c_state)idle:beginif(a == 0)n_state = state1;elsen_state = idle;endstate1:beginif(a == 1)n_state = state2;elsen_state = state1;endstate2:beginif(a == 1)n_state = state3;elsen_state = state1;endstate3:beginif(cnt == 2)n_state = state4;elsen_state = state3;endstate4:beginif(a == 1)n_state = state5;elsen_state = state1;endstate5:beginif(a == 1)n_state = state6;elsen_state = state1;endstate6:beginif(a == 0)n_state = state7;elsen_state = idle;endstate7:beginif(a == 1)n_state = idle;elsen_state = state1;enddefault:n_state = idle;endcaseendalways@(posedge clk or negedge rst_n)beginif(!rst_n)cnt <= 2'b0;else if(c_state == state3 && cnt == 2'd3)cnt <= 2'b0;else if(c_state == state3)cnt <= cnt + 1'b1;elsecnt <= 2'b0;endalways@(posedge clk or negedge rst_n)beginif(!rst_n)match <= 1'b0;else if(c_state == state7)match <= 1'b1;elsematch <= 1'b0;end endmodule

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