*PN512寄存器設置數組
code unsigned char CardTypeSetReg[][5]={{0x08,0,0x08,0x08,0x08},Status2Reg,turn off crypto
{0x0C,1,0x10,0x10,0x10},ControlReg,pn512 act as initiator
{0x11,2,0x38,0x39,0x3B},ModeReg,crcpreset
{0x12,2,0x92,0x00,0x83},TxModeReg,txcrc enable,felica at 212kbps,mifare106,typeb106
{0x13,2,0x92,0x00,0x83},RxModeReg,rxcrc enable,felica at 212kbps,mifare106,typeb106
{0x14,2,0x83,0x83,0x83},TxControlReg,tx2 inverted,tx1 and tx2 out enable
{0x15,2,0x00,0x40,0x00},TxAutoReg,antenna setting,100% ask disable for felica and typeb
{0x16,2,0x10,0x10,0x10},TxSelReg,tx output from internal coder
{0x17,2,0x84,0x86,0x86},RxSelReg,rxwait,felica=4,14443=6{0x18,2,0x55,0x84,0x44},RxThresholdReg,set minlevel and collevel,when use rc531,typea=0xff(max),typeb=0x44{0x19,2,0x41,0x4D,0x4D},DemodReg,Defines demodulator,when use rc531,TAU=E{0x1A,2,0x00,0x00,0x00},FelNFC1Reg,Defines the length of the FeliCa Sync bytes and the minimum length of the received packet
{0x1D,2,0x11,0x10,0x10},ManualRCVReg,Parity Disable,High Pass Corner Frequency spectrum down to 212 kHz for felica,14443set to 106kbps
{0x1E,2,0x00,0x00,0x90},TypeBReg,typeB settings
{0x23,2,0x88,0x88,0x88},GsNOffReg,Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched off
{0x24,2,0x26,0x26,0x26},ModWidthReg,Controls the modulation width settings,rc531=0x13{0x26,2,0x79,0x7F,0x79},RFCfgReg,Configures the receiver gain and RF level detector sensitivity
{0x27,2,0x88,0x88,0x88},GsNOnReg,Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on
{0x28,2,0x30,0x20,0x20},CWGsPReg,Defines the conductance of the P-driver during times of no modulation
{0x29,2,0x06,0x06,0x06} ModGsPReg,Defines the driver P-output conductance during modulation,不大于10可讀,對讀卡距離影響非常大
}; 第一列是寄存器地址;第二列為寄存器設置方法:0表示清0對應位,1表示置1對應位,2表示直接寫入;第三列是操作FELICA設置值;第四列是操作ISO/IEC14443A/MIFARE設置值;第五列是操作ISO/IEC14443B設置值。
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