SystemInit（）函數(shù)：

void SystemInit (void) {/* Set HSION bit */RCC->CR |= (uint32_t)0x00000001;//把內(nèi)部的HSI RC（高速時鐘）打開#ifndef STM32F10X_CLRCC->CFGR &= (uint32_t)0xF8FF0000;//這一句不會執(zhí)行，由于定義的是STM32F10X_HD，他會執(zhí)行else后的語句。 #elseRCC->CFGR &= (uint32_t)0xF0FF0000;//系統(tǒng)初始化狀態(tài) #endif /* STM32F10X_CL */ /* Reset HSEON, CSSON and PLLON bits */RCC->CR &= (uint32_t)0xFEF6FFFF;//默認狀態(tài)/* Reset HSEBYP bit */RCC->CR &= (uint32_t)0xFFFBFFFF;//默認狀態(tài)/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */RCC->CFGR &= (uint32_t)0xFF80FFFF;//默認狀態(tài)#ifdef STM32F10X_CL/* Reset PLL2ON and PLL3ON bits */RCC->CR &= (uint32_t)0xEBFFFFFF;/* Disable all interrupts and clear pending bits */RCC->CIR = 0x00FF0000;/* Reset CFGR2 register */RCC->CFGR2 = 0x00000000; #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)/* Disable all interrupts and clear pending bits */RCC->CIR = 0x009F0000;/* Reset CFGR2 register */RCC->CFGR2 = 0x00000000; //由于是STM32F10X_CL，所以ifdef后的語句不會執(zhí)行 #else/* Disable all interrupts and clear pending bits */RCC->CIR = 0x009F0000;//把所有中斷都關(guān)掉，位全部都清掉 #endif /* STM32F10X_CL */#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)#ifdef DATA_IN_ExtSRAMSystemInit_ExtMemCtl(); //這里沒有執(zhí)行，因為不是STM32F10X_HD#endif /* DATA_IN_ExtSRAM */ #endif /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers *//* Configure the Flash Latency cycles and enable prefetch buffer */SetSysClock();#ifdef VECT_TAB_SRAMSCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #elseSCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ #endif }

SystemInit（）中的SetSysClock()函數(shù)部分：

static void SetSysClock(void) { #ifdef SYSCLK_FREQ_HSESetSysClockToHSE(); #elif defined SYSCLK_FREQ_24MHzSetSysClockTo24(); #elif defined SYSCLK_FREQ_36MHzSetSysClockTo36(); #elif defined SYSCLK_FREQ_48MHzSetSysClockTo48(); #elif defined SYSCLK_FREQ_56MHzSetSysClockTo56(); #elif defined SYSCLK_FREQ_72MHz//這里的意思是判斷標(biāo)識符有沒有被定義，定義了哪種就調(diào)用哪種設(shè)置系統(tǒng)時鐘的函數(shù)。SetSysClockTo72(); #endif/* If none of the define above is enabled, the HSI is used as System clocksource (default after reset) */ }

這里是舉例SetSysClockTo72()這個系統(tǒng)時鐘函數(shù)：
FLASH_ACR是閃存訪問控制寄存器

static void SetSysClockTo72(void) {__IO uint32_t StartUpCounter = 0, HSEStatus = 0;/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON);//外部高速時鐘使能/* Wait till HSE is ready and if Time out is reached exit do while語句意思是等待HSE穩(wěn)定 */do{HSEStatus = RCC->CR & RCC_CR_HSERDY;StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));if ((RCC->CR & RCC_CR_HSERDY) != RESET){HSEStatus = (uint32_t)0x01;//HSEStatus是表示一種狀態(tài)}//if語句是判斷是否準(zhǔn)備就緒else{HSEStatus = (uint32_t)0x00;} if (HSEStatus == (uint32_t)0x01)//就緒后執(zhí)行這一步{/* Enable Prefetch Buffer */FLASH->ACR |= FLASH_ACR_PRFTBE;///* Flash 2 wait state */FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; //cpu的速度比芯片的flash的速度快很多，所以在操作之前要等待時鐘，這三句是對FLASH_ACR寄存器操作/* HCLK = SYSCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;//HCLK = SYSCLK就要設(shè)置AHB預(yù)分頻為不分頻 /* PCLK2 = HCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;//PCLK2 = HCLK就要APB2預(yù)分頻預(yù)分頻系數(shù)HCLK不分頻/* PCLK1 = HCLK/2*/RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;//PCLK1 = HCLK/2就要APB1設(shè)置預(yù)分頻系數(shù)HCLK的二分頻 #ifdef STM32F10X_CL/* Configure PLLs ------------------------------------------------------*//* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz *//* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);/* Enable PLL2 */RCC->CR |= RCC_CR_PLL2ON;/* Wait till PLL2 is ready */while((RCC->CR & RCC_CR_PLL2RDY) == 0){}/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9); #else /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |RCC_CFGR_PLLMULL));RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);//RCC_CFGR_PLLSRC_HSE是將HSE作為PLL的時鐘源，RCC_CFGR_PLLMULL9是將倍頻系數(shù)設(shè)置為9 #endif /* STM32F10X_CL *//* Enable PLL */RCC->CR |= RCC_CR_PLLON;//使能PLL時鐘/* Wait till PLL is ready while語句等待PLL就緒*/while((RCC->CR & RCC_CR_PLLRDY) == 0){}/* Select PLL as system clock source 將PLL作為系統(tǒng)時鐘來源*/RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08){}}else{ /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */} }

總結(jié)一下：
SystemInit()函數(shù)中設(shè)置的系統(tǒng)時鐘大小：

SYSCLK（系統(tǒng)時鐘） =72MHzAHB 總線時鐘(使用 SYSCLK) =72MHzAPB1 總線時鐘(PCLK1) =36MHzAPB2 總線時鐘(PCLK2) =72MHzPLL 時鐘 =72MHz

總結(jié)

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