一、設計要求
東西方向和南北方向各有 紅黃綠三盞燈
其中紅燈30秒 黃燈5秒 綠燈25秒

二、設計代碼
traffic_led.v

module traffic_led(rst_n,clk,r1,g1,y1,r2,g2,y2);//c5,c25,c30????????ˉ??‰??a????—???¨???è?“??o? ???—???,en????????ˉ??‰??a????—???¨??????è?????input rst_n,clk;wire c5,c25,c30;reg [2:0] en;output reg r1,g1,y1,r2,g2,y2; //è?“??o??ˉ??￡è???’?è?“? ￥??ˉ??￡é“???￥??—???reg [3:0] current_state,next_state;localparam s0 = 4'b0001,s1 = 4'b0010,s2 = 4'b0100,s3 = 4'b1000;clock_5 u0(.clk(clk),.rst_n(rst_n),.en5(en[0]),.c5(c5));clock_25 u1(.clk(clk),.rst_n(rst_n),.en25(en[1]),.c25(c25));clock_30 u2(.clk(clk),.rst_n(rst_n),.en30(en[2]),.c30(c30));always @(posedge clk or negedge rst_n)beginif(!rst_n)begincurrent_state <= s0;endelsecurrent_state <= next_state; endalways@(*)begincase(current_state)s0:begin //?”2é€?è???1??|??-￠en <= 3'b100;r1 <= 1'b0; r2 <= 1'b1;g1 <= 1'b1; g2 <= 1'b0;y1 <= 1'b0; y2 <= 1'b0;if(c30 == 1)next_state <= s1;elsenext_state <= s0;ends1:begin //?”2???????1??|??-￠en <= 3'b001;r1 <= 1'b0; r2 <= 1'b1;g1 <= 1'b0; g2 <= 1'b0;y1 <= 1'b1; y2 <= 1'b0;if(c5 == 1)next_state <= s2;else next_state <= s1; ends2:begin //?”2?|??-￠?1?é€?è??en <= 3'b010;r1 <= 1'b1; r2 <= 1'b0;g1 <= 1'b0; g2 <= 1'b1;y1 <= 1'b0; y2 <= 1'b0;if(c25 == 1)next_state <= s3;elsenext_state <= s2; ends3:begin //?”2?|??-￠?1???????en <= 3'b001;r1 <= 1'b1; r2 <= 1'b0;g1 <= 1'b0; g2 <= 1'b0;y1 <= 1'b0; y2 <= 1'b1;if(c5 == 1)next_state <= s0;elsenext_state <= s3;enddefault: next_state <= s0;endcaseend endmodule

五秒黃燈延時
clock_5.v

module clock_5(clk,rst_n,en5,c5);input clk,rst_n,en5;output reg c5;reg [17:0] cnt5;//5ms = 5_000us = 5_000_000ns/20 = 250_000 = 18bitalways @(posedge clk or negedge rst_n)beginif(!rst_n)begincnt5 <= 18'd0;//c5 <= 1'b0;endelse if(en5 == 1'b1)beginif(cnt5 == 18'd249_999)//249_999begincnt5 <= 18'd0;//c5 <= 1'b1;endelsebegincnt5 <= cnt5 + 1'b1;c5 <= 1'b0;endend elsecnt5 <= 18'd0;end endmodule

25秒綠燈延時
25_clock.v

module clock_25(clk,rst_n,en25,c25);input clk,rst_n,en25;output reg c25;reg [20:0] cnt25;//25ms = 25_000us = 25_000_000ns/20 = 1250_000 = 21bitalways @(posedge clk or negedge rst_n)beginif(!rst_n)begincnt25 <= 21'd0;//c25 <= 1'b0;endelse if(en25 == 1'b1)beginif(cnt25 == 21'd1249_999)//1499_999_999begincnt25 <= 21'd0;c25 <= 1'b1;endelsebegincnt25 <= cnt25 + 1'b1;c25 <= 1'b0;endend elsecnt25 <= 21'd0;endendmodule

30秒紅燈延時
clock_30.v

module clock_30(clk,rst_n,en30,c30);input clk,rst_n,en30;output reg c30;reg [20:0] cnt30;//30ms = 30_000us = 30_000_000ns/20 = 1500_000 = 21bitalways @(posedge clk or negedge rst_n)beginif(!rst_n)begincnt30 <= 21'd0;//c30 <= 1'b0;endelse if(en30 == 1'b1)beginif(cnt30 == 21'd1499_999)//1499_999_999begincnt30 <= 21'd0;//c30 <= 1'b1;endelsebegincnt30 <= cnt30 + 1'b1;c30 <= 1'b0;endend elsecnt30 <= 21'd0;endendmodule

激勵代碼
traffic_led_tb.v

timescale 1ns/1ns `define clock_period 20module traffic_led_tb;reg clk,rst_n;wire r1,r2,g1,g2,y1,y2;traffic_led utb(.rst_n(rst_n),.clk(clk),.r1(r1),.g1(g1),.y1(y1),.r2(r2),.g2(g2),.y2(y2));initial clk = 1;always #(`clock_period/2) clk = ~clk;initial beginrst_n = 1'b0;#(`clock_period*5+5);rst_n = 1'b1;endendmodule

三、modelsim仿真波形圖

四、Verilog仿真引腳圖、RTL圖

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