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Verilog | HDL 音乐流水灯(代码类)

發(fā)布時(shí)間:2025/3/12 编程问答 27 豆豆
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博主github:https://github.com/MichaelBeechan
博主CSDN:https://blog.csdn.net/u011344545

module beyond(clk,beep,led); input clk; output beep; output [7:0]led; reg beep; reg [22:0]i; reg clk_4hz; reg [7:0]led; reg [16:0] count,div_num;// reg [6:0] music;//just for a test; always @(posedge clk)//4hz begin if(i==23'h47868c) begin i<=0; clk_4hz=~clk_4hz; end else i=i+1'b1; end always @(posedge clk_4hz) begin if(music==7'd90)notice music<=0; else music<=music+1'b1; end always @(posedge clk) begin if(count==div_num) begin count<=0; beep=~beep; end else count<=count+1'b1; end parameter? L1=17'h1754e, L2=17'h14c81, L3=17'h1284a, L4=17'h117A8, L5=17'h14e70, L6=17'h0ddf2, L7=17'h0c5ba, M1=17'h0ba9e, M2=17'h0a648, M3=17'h0941f, M4=17'h08bcf, M5=17'h07c90, M6=17'h06ef9, M7=17'h062dd, H1=17'h05d68, H2=17'h05322, H3=17'h04a11, H4=17'h045e9, H5=17'h3e48, H6=17'h377d, H7=17'h316f; always @(posedge clk_4hz) begin case(music) 7'd0 : div_num=M7; 7'd1 : div_num=M7; 7'd2 : div_num=H1; 7'd3 : div_num=H1; 7'd4 : div_num=H2; 7'd5 : div_num=H2; 7'd6 : div_num=H2; 7'd7 : div_num=H3; 7'd8 : div_num=H3; 7'd9 : div_num=H3; 7'd10 : div_num=H3; 7'd11 : div_num=H2; 7'd12 : div_num=H2; 7'd13 : div_num=H2; 7'd14 : div_num=H2; 7'd15 : div_num=H2; 7'd16 : div_num=H1; 7'd17 : div_num=M7; 7'd18 : div_num=M5; 7'd19 : div_num=M6; 7'd20 : div_num=M6; 7'd21 : div_num=M6; 7'd22 : div_num=M3; 7'd23 : div_num=M2; 7'd24 : div_num=M3; 7'd25 : div_num=M3; 7'd26 : div_num=M3; 7'd27 : div_num=M3; 7'd28 : div_num=M5; 7'd29 : div_num=M5; 7'd30 : div_num=M5; 7'd31 : div_num=M6; 7'd32 : div_num=M6; 7'd33 : div_num=M6; 7'd34 : div_num=H1; 7'd35 : div_num=M7; 7'd36 : div_num=H1; 7'd37 : div_num=H1; 7'd38 : div_num=H7; 7'd39 : div_num=H7; 7'd40 : div_num=H1; 7'd41 : div_num=H1; 7'd42 : div_num=H1; 7'd43 : div_num=H1; //repeat 7'd44 : div_num=M7; 7'd45 : div_num=M7; 7'd46 : div_num=H1; 7'd47 : div_num=H1; 7'd48 : div_num=H2; 7'd49 : div_num=H2; 7'd50 : div_num=H2; 7'd51 : div_num=H3; 7'd52 : div_num=H3; 7'd53 : div_num=H3; 7'd54 : div_num=H3; 7'd55 : div_num=H2; 7'd56 : div_num=H2; 7'd57 : div_num=H2; 7'd58 : div_num=H2; 7'd59 : div_num=H2; 7'd60 : div_num=H1; 7'd61 : div_num=M7; 7'd62 : div_num=H1; 7'd63 : div_num=H1; 7'd64 : div_num=M7; 7'd65 : div_num=M7; 7'd66 : div_num=M7; 7'd67 : div_num=M7; 7'd68 : div_num=M3; 7'd69 : div_num=M2; 7'd70 : div_num=M3; 7'd71 : div_num=M3; 7'd72 : div_num=M3; 7'd73 : div_num=M3; 7'd74 : div_num=M5; 7'd75 : div_num=M5; 7'd76 : div_num=M5; 7'd77 : div_num=M6; 7'd78 : div_num=M6; 7'd79 : div_num=M6; 7'd80 : div_num=L5; 7'd81 : div_num=L6; 7'd82 : div_num=M1; 7'd83 : div_num=M2; 7'd84 : div_num=M3; 7'd85 : div_num=M5; 7'd86 : div_num=H1; 7'd87 : div_num=H1; 7'd88 : div_num=H1; 7'd89 : div_num=H1; endcase end always @(div_num) begin case(div_num) L5 : led=8'b1111_1111; L6 : led=8'b0111_1111; L7, M1 : led=8'b0011_1111; M2, M3 : led=8'b0001_1111; M4, M5 : led=8'b0000_1111; M6, M7 : led=8'b0000_0111; H1 : led=8'b0000_0011; H2 : led=8'b0000_0001; H3 : led=8'b0000_0000; default : led=8'bx; endcase endendmodule// Copyright (C) 1991-2008 Altera Corporation // Your use of Altera Corporation's design tools, logic functions? // and other software and tools, and its AMPP partner logic? // functions, and any output files from any of the foregoing? // (including device programming or simulation files), and any? // associated documentation or information are expressly subject? // to the terms and conditions of the Altera Program License? // Subscription Agreement, Altera MegaCore Function License? // Agreement, or other applicable license agreement, including,? // without limitation, that your use is for the sole purpose of? // programming logic devices manufactured by Altera and sold by? // Altera or its authorized distributors. ?Please refer to the? // applicable agreement for further details.// Generated by Quartus II Version 8.0 (Build Build 231 07/10/2008) // Created on Sun Dec 22 11:38:33 2013beyond beyond_inst ( .clk(clk_sig) , // input ?clk_sig .beep(beep_sig) , // output ?beep_sig .led(led_sig) // output [7:0] led_sig );defparam beyond_inst.L1 = 'b10111010101001110; defparam beyond_inst.L2 = 'b10100110010000001; defparam beyond_inst.L3 = 'b10010100001001010; defparam beyond_inst.L4 = 'b10001011110101000; defparam beyond_inst.L5 = 'b10100111001110000; defparam beyond_inst.L6 = 'b01101110111110010; defparam beyond_inst.L7 = 'b01100010110111010; defparam beyond_inst.M1 = 'b01011101010011110; defparam beyond_inst.M2 = 'b01010011001001000; defparam beyond_inst.M3 = 'b01001010000011111; defparam beyond_inst.M4 = 'b01000101111001111; defparam beyond_inst.M5 = 'b00111110010010000; defparam beyond_inst.M6 = 'b00110111011111001; defparam beyond_inst.M7 = 'b00110001011011101; defparam beyond_inst.H1 = 'b00101110101101000; defparam beyond_inst.H2 = 'b00101001100100010; defparam beyond_inst.H3 = 'b00100101000010001; defparam beyond_inst.H4 = 'b00100010111101001; defparam beyond_inst.H5 = 'b00011111001001000; defparam beyond_inst.H6 = 'b00011011101111101; defparam beyond_inst.H7 = 'b00011000101101111;

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