8086簡(jiǎn)單的指令流水線

Any computer or machine works according to some instructions. These instructions are responsible for all the work that the machine does. But how does a machine work to understand and execute that instruction?

任何計(jì)算機(jī)或機(jī)器都按照某些說明工作。 這些說明負(fù)責(zé)機(jī)器的所有工作。 但是，機(jī)器如何工作才能理解并執(zhí)行該指令？

In the 8086 microprocessors, the instructions are executed in 4 steps which are listed as follows:

在8086微處理器中， 指令按4個(gè)步驟執(zhí)行，列出如下：

Fetch the instruction

獲取指令

Decode the instruction

解碼指令

Fetch the operands

提取操作數(shù)

Execution of the instruction

指令的執(zhí)行

Any instruction that is provided to the 8086 microprocessor is executed by following the above-mentioned steps. For each instruction, all these steps are performed, i.e. if there are 3 instructions to be executed, then all these steps will be performed 3 times each.

通過遵循上述步驟，可以執(zhí)行提供給8086微處理器的任何指令。 對(duì)于每個(gè)指令，將執(zhí)行所有這些步驟，即，如果要執(zhí)行3條指令，則所有這些步驟將分別執(zhí)行3次。

Suppose, these instructions are executed sequentially, and it takes the 1-time unit for each step to run. So, it would take 12-time units (3 X 4) to execute these instructions.

假設(shè)這些指令是按順序執(zhí)行的，并且每步運(yùn)行需要1單位時(shí)間。 因此，執(zhí)行這些指令將需要12倍的時(shí)間(3 X 4)。

It seems less as the number of instructions is less, but a processor has o deal with a very large number of instructions, and so it should process fast to be efficient. In the 8086 microprocessor, this problem was solved by the method of pipelining.

指令數(shù)量越少，似乎就越少，但是處理器可以處理大量指令，因此它應(yīng)該快速處理以提高效率。 在8086微處理器中，此問題通過流水線方法解決。

As we know that there are two separate units in 8086 microprocessors:

我們知道8086微處理器中有兩個(gè)獨(dú)立的單元：

The BIU (Bus Interface Unit)

BIU(總線接口單元)

The EU (Execution unit)

歐盟(執(zhí)行單位)

Both these units work mutually exclusive to each other. Due to this, the parallel processing of instructions can be implied in the 8086 microprocessor, because these units are responsible for alternate steps of instruction execution. That is,

這兩個(gè)單元相互排斥。 因此，可以在8086微處理器中隱含指令的并行處理，因?yàn)檫@些單元負(fù)責(zé)指令執(zhí)行的替代步驟。 那是，

• Fetch instruction: Done by BIU

  提取指令：由BIU完成

• Decode Instruction: Done by EU

  解碼說明：歐盟完成

• Fetch Operands: Done by BIU

  獲取操作數(shù)：由BIU完成

• Execution: Done by EU

  執(zhí)行：由歐盟完成

So, while the instruction completes its first step and goes to the second step that is handled by the EU, the BIU is idle, and in that time, the next instruction is sent to BIU. By doing so, the parallel processing of instructions is implemented, and this concept is known as pipelining.

因此，當(dāng)指令完成其第一步并轉(zhuǎn)到由EU處理的第二步時(shí)，BIU處于空閑狀態(tài)，此時(shí)，下一條指令被發(fā)送到BIU。 通過這樣做，實(shí)現(xiàn)了指令的并行處理，并且該概念被稱為流水線。

So, it can be observed that the instructions which were taking 12-time units for execution while being processed in a sequential way are now taking only 6 clock cycles through pipelining.

因此，可以觀察到以流水線方式執(zhí)行的指令在以順序方式進(jìn)行處理時(shí)占用了12個(gè)時(shí)間單元，而現(xiàn)在僅需要6個(gè)時(shí)鐘周期。

翻譯自: https://www.includehelp.com/embedded-system/steps-to-execute-an-instruction-and-concept-of-pipelining-in-8086-microprocessors.aspx

8086簡(jiǎn)單的指令流水線

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