用于新PCB板調試開發，在系統最開始（內存初始化之前），盡快打印字符，驗證CPU是否正常啟動。

以freescale QorIQ 處理器兼容的UART為例，符合16550串口標準：

/*UART DEBUG*/

/*
#define CCSBAR_RESET??????????? 0xff700000
#define CCSBAR????????????????? 0xf3000000
*/

#define DUART_BLOCK_BASE 0x4000
#define UART0_REG_BASE???????? (CCSBAR???? +?? DUART_BLOCK_BASE+0x500)?
#define UART1_REG_BASE???????? (CCSBAR???? +?? DUART_BLOCK_BASE+0x600)?

#define LCR_DLAB?0x80?/* divisor latch access enable */
#define DLAB??LCR_DLAB

/*UART0 baudrate: 115200 . Refer to : ns16550sio.c */
/*?
For P1020?board: xtal = CCB clk = 266M Hz, core0 = 2*CCB = 533.
divisor = ((pChan->xtal + (8 * baud)) / (16 * baud))
??????? = (pChan->xtal / ( 8UL * baud ) + 1) / 2
??????? = (266000000 / (8*115200)? +1 )/2
??????? = 144.8 = 145 = 0x0091

For?P2020 brd, it is 600MHz (sysClkFreqGet()), divisor = 0x146.
*/

??? /*-------- enable DLAB. begin --------*/
??? lis? r6, HIADJ(UART0_REG_BASE)
??? ori r6, r6, LO(UART0_REG_BASE)
??? lbz? r4, 3(r6)? /*read Reg LCR*/
??? ori? r4, r4, LCR_DLAB
??? stb? r4, 3(r6)? /*write Reg LCR. Enable DLAB */
?msync
?isync
?/*-------- enable DLAB. end? --------*/

??? /*------- set baud rate. begin ------*/
??? li?? r7, 0x46?? /*divisor low byte*/
??? stb? r7, 0(r6)
??? msync
?isync
?
??? li?? r7, 0x01? /*divisor high byte*/
??? stb? r7, 1(r6) /*set baud rate: 115200*/
?msync
?isync
??? /*------- set baud rate. end? ------*/

??? /*------- set options. begin -------*/
??? li r7, 0x03
??? stb r7, 3(r6) /*set options in reg LCR : 8-N-1-none*/
?msync
?isync
?/*------- set options. end -------*/

?
??? /*------- Write information to UART port. begin ------*/
?li?? r7, 0x55 /*U*/
??? stb? r7, 0(r6)
??? msync
?isync
?li?? r7, 0x79 /*y*/
??? stb? r7, 0(r6)
??? msync
?isync
?/*------- End to write. -----*/

?

轉載于:https://www.cnblogs.com/sincos/p/3960563.html

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