PLL详细设计方案
1.????? PLL簡介：
PLL(Phase Locked Loop)：為鎖相回路或鎖相環,用來統一整合時脈訊號,使內存能正確的存取資料。PLL用于振蕩器中的反饋技術。
鎖相環是一種反饋電路，其作用是使得電路上的時鐘和某一外部時鐘的相位同步。PLL通過比較外部信號的相位和由壓控晶振（VCXO）的相位來實現同步的，在比較的過程中，鎖相環電路會不斷根據外部信號的相位來調整本地晶振的時鐘相位，直到兩個信號的相位同步。
2.????? PLL規格：
輸出
100M
20M
80M
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3個時鐘頻率
3.????? 實現原理
使用ALTERA PLL例化得到。
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4.????? Verilog HDL源代碼
Verilog HDL代碼為：
modulePLL_Inst (
????????????? //input
????????????? sys_clk??????? ,
????????????? sys_rst_n????? ,
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????????????? //output
????????????? clk_100M?????? ,
????????????? clk_20M??????? ,
???????????? ?clk_80M???????
????????????? // data_out
????????????? );
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//inputports
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input??????????????????? sys_clk???????????? ;??? //system clock;
input??????????????????? sys_rst_n?????????? ;???//system reset, low is active;
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//outputports
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output??????? ???????????clk_100M??????????? ;???//output clock 100M;?
output?????????????????? clk_20M???????????? ;??? //output clock 20M;?
output?????????????????? clk_80M???????????? ;??? //output clock 80M;?
//output?????????????????? clock_enbale??????? ;
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//regdefine
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//wiredefine
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wire???????????????????? clk_100M_tmp??????? ;???//wire clock 100M;?
wire???????????????????? clk_80M_tmp???????? ;???//wire clock 20M;?
wire???????????????????? clk_20M_tmp???????? ;???//wire clock 80M;?
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wire??????????? ?????????clk_100M??????????? ;???//wire clock 100M;?
wire???????????????????? clk_80M???????????? ;??? //wire clock 20M;?
wire???????????????????? clk_20M???????????? ;??? //wire clock 80M;?
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//parameterdefine
parameterWIDTH = 8;
parameterSIZE? = 8;
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/*******************************************************************************************************
**????????????????????????????? Main Program???
**?
********************************************************************************************************/
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//instancethe PLL
PLL?? PLL_U0???(
?????? ????????????? .areset? (sys_rst_n??????? )???????????? ,
?????? ????????????? .inclk0? (sys_clk????????? )???????????? ,
?????? ????????????? .c0????? (clk_100M_tmp???? )???????????? ,
?????? ????????????? .c1????? (clk_20M_tmp????? )???????????? ,
?????? ????????????? .c2????? (clk_80M_tmp????? )???????????? ,
?????? ????????????? .locked? (clock_enbale???? )????????????
?????? ????????????? );
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//enbalethe clock when the pll is locked
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assignclk_100M = (clock_enbale == 1'b1)? clk_100M_tmp : 1'b0;
assignclk_80M? = (clock_enbale == 1'b1)?clk_80M_tmp? : 1'b0;
assignclk_20M? = (clock_enbale == 1'b1)?clk_20M_tmp? : 1'b0;
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endmodule
//endof RTL code ??
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