频率及占空比检测
項(xiàng)目名稱:
頻率計(jì)設(shè)計(jì)
具體要求:
檢測(cè)方波的頻率和占空比
設(shè)計(jì)架構(gòu)
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??
wave:方波輸入
freq:檢測(cè)出的方波頻率
duty_cycle:測(cè)試出的方波占空比
狀態(tài)轉(zhuǎn)移圖
測(cè)試出高電平和低電平的時(shí)間,經(jīng)過(guò)計(jì)算得出頻率和占空比
high_state:高電平狀態(tài)
low_state:低電平狀態(tài)
low_cnt:低電平計(jì)數(shù)
high_cnt:高電平計(jì)數(shù)
low_time:低電平時(shí)間
high_time:高電平時(shí)間
代碼設(shè)計(jì)
verilog代碼設(shè)計(jì)
module freq_detect(input clk,input rst_n,input wave,output [25:0] freq, //檢測(cè)方波的頻率output [6:0] duty_cycle //檢測(cè)方波的占空比 );reg state; localparam high_state=1'd0; localparam low_state=1'd1; reg [25:0]high_cnt;//可測(cè)試到1hz reg [25:0]low_cnt; reg [25:0]high_time; reg [25:0]low_time; always@(posedge clk or negedge rst_n)if(!rst_n)beginstate<=high_state;high_cnt<=26'd0;low_cnt<=26'd0;high_time<=26'd0;low_time<=26'd0;endelse begincase(state)high_state: beginif(wave==1)beginhigh_cnt<=high_cnt+1'b1;state<=high_state;endelse beginhigh_cnt<=26'd0;high_time<=high_cnt;state<=low_state;endendlow_state : beginif(wave==0)beginlow_cnt<=low_cnt+1'b1;state<=low_state;endelse beginlow_time<=low_cnt;low_cnt<=26'd0;state<=high_state;endenddefault:state<=high_state;endcaseend //系統(tǒng)時(shí)鐘為50Mhz,計(jì)數(shù)需要時(shí)間=計(jì)數(shù)值*20ns,測(cè)試頻率的周期為high_time*20+low_time*20 assign freq=1000_000_000/(high_time*20+low_time*20); //占空比乘以100之后化為0-100之間的整數(shù) assign duty_cycle=high_time*100/(high_time+low_time); endmodule仿真代碼
`timescale 1ns/1ns module freq_detect_tb;reg clk;reg rst_n;reg wave;wire [25:0] freq; //檢測(cè)方波的頻率wire [6:0] duty_cycle; //檢測(cè)方波的占空比f(wàn)req_detect freq_detect(.clk(clk),.rst_n(rst_n),.wave(wave),.freq(freq), //檢測(cè)方波的頻率.duty_cycle(duty_cycle) //檢測(cè)方波的占空比 );initial clk=0; always #10 clk=~clk;initial beginrst_n=0;#200rst_n=1;#1_000_000_0 //仿真時(shí)間10ms$stop; endinitial beginwave=1;forever begin //產(chǎn)生占空比為60%,1khz的方波#600_000;wave=0;#400_000;wave=1;end endendmodule仿真結(jié)果
從結(jié)果可以看出待輸出穩(wěn)定之后,檢測(cè)出1000hz的方波,待測(cè)試的方波在第二個(gè)周期可以穩(wěn)定檢測(cè)到占空比60%,代碼中將檢測(cè)到的占空比乘以100,得到60.
總結(jié)
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