1. 配置需求

• 時(shí)鐘輸入：SCKI（24.576MHz）
• 模擬輸入：VINL2（Stereo left channel）,VINR2（Stereo right channel）
• LRCK：96KHz
• BCK：6.14MHz

2. 配置通信接口

In software SPI/I2C mode, a PCM186x software programmable device can use its on-chip crystal oscillator, if a CMOS clock source is not available.

通信口選擇I2C：

2.1. I2C地址

8bit I2C地址（b100101’AD”R/W’, 0x94 or 0x96）

2.2. 通信時(shí)序

3. 配置時(shí)鐘源

If an external, high quality MCLK is available (either on the SCK pin or XTAL), then the PCM186x should be configured to run in Master Mode where possible, with the ADC and serial ports being driven from the MCLK/SCK source. The on-chip DSPs will continue to require clocks from the PLL, as they run from a much higher clock rate.

Clock MUXs and overall configuration can be done in register Page0, 0x20. For the best performance in master mode, where possible, the automatic clock configuration circuitry will configure the clocks as shown in Table 9, depending on if the device is a PCM186x software programmable device. The tables below show data at 48kHz multiples, the ratios for multiples of 44.1kHz are identical, while the absolute MHz values will be multiples of 44.1kHz instead of 48kHz.

This automatic configuration can be bypassed using registers, starting from CLKDET_EN (Page.0, 0x20).

PCM1863工作在軟件可編程模式

3.1. 配置時(shí)鐘源寄存器0x20

• 設(shè)置成主模式
  
• 選擇外部時(shí)鐘源SCKI
  
• 默認(rèn)使能CLKDET_EN，打開自動(dòng)配置模式，因此不需要配置ADC_CLK_SRC、DSP2_CLK_SRC、DSP1_CLK_SRC
• 配置BCK, LRCK的時(shí)鐘頻率
  
  如上圖所示，在master mode時(shí)，配置0x26, 0x27寄存器，可以得到想要的BCK和LRCK的速率。查詢Table 9，可得知當(dāng)輸入時(shí)鐘SCK Frequence是24.576MHz時(shí)，可用的采樣頻率有48K，96K，192K，采樣頻率等于LRCK速率。
  
  
  • LRCK=96KHz=SCKFrequence/CLKDIVMSTSCK(Reg0x26)/CLKDIVMSTBCK(Reg0x27)
  • BCK=6.14M=SCKFrequence/CLKDIVMSTSCK(Reg0x26)
  • 將SCK Frequence = 24.576MHz帶入上述公式，可得CLK_DIV_MST_SCK = 4，CLK_DIV_MST_BCK=64

3.2. 配置SCK寄存器0x26, 0x27

4. 配置輸入和輸出

• PCM1863支持最多4路模擬輸入+1路雙聲道I2S輸入，支持1路雙聲道I2S輸出
• 雙聲道I2S輸入需要和PM1863共用一組I2S時(shí)鐘

4.1. 配置首要模擬音頻信號(hào)輸入源

• 本設(shè)計(jì)使用VINL2和VINR2作為模擬輸入源，沒有使用模擬麥克風(fēng)和數(shù)字麥克風(fēng)
• 關(guān)閉mic bias，配置寄存器0x15
  
  
• 配置寄存器0x06，0x07
  
  

4.2. 配置次要模擬信號(hào)輸入源

The secondary ADC has two main purposes in the PCM186x family. The primary purpose is to act as a low power signal detection system, to aid with system wakeup from sleep. TI calls this functionality “Energysense”.

• 改變SGIDET_CH_Mode的值可以在Energysense和Controlsense這兩個(gè)模式之間切換，默認(rèn)配置為Energysense
• 次要模擬輸入的輸入范圍是0-1.65V
• 次要模擬輸入通道配置為不選擇

4.3. 配置I2S信號(hào)輸入

本設(shè)計(jì)沒有使用I2S輸入，可以直接使用寄存器0x08的默認(rèn)配置：

4.4. 配置I2S信號(hào)輸出

配置I2S格式，寄存器0x08的默認(rèn)配置：

4.5. 配置輸出mixer

This function allows post ADC mixing, as well as ADC + incoming I2S mix. Volume control functionality can be performed prior to outputting the signal to an I2S DAC or Amplifier.

Gain range is from –100dB to + 18dB (20 bits negative up +18dB, 4.20 format).

As the DSP coefficients are directly written, no soft ramping is available. Use of I2S receive sacrifices 2 digital mic channels due to pin limitations.

Coefficients are written indirectly to virtual memory addresses using the registers on Page 1.

5. 其他配置

• 配置自動(dòng)削波抑制：此功能的作用是在檢測到削波發(fā)生時(shí)，自動(dòng)降低模擬輸入的增益，默認(rèn)是關(guān)閉的。
• 模擬音頻輸入信號(hào)強(qiáng)度檢測：可以用作睡眠喚醒（最低可檢測到的信號(hào)強(qiáng)度是-57dBdBFS）。
• 未用作音頻輸入的模擬輸入：可用來檢測直流電壓的改變，其值可以通過讀取I2C寄存器獲取。
• GPIO配置：可用作中斷輸出腳，也可用作一般GPIO腳。

6. 示例代碼

const uint8_t IIC_REG_1863[IIC_REG_1863_SIZE][2] = { /* Page 0 Configuration */{0x00,0x00}, /* Register page selection = page 0 */{0x05,0x9b}, /* PGA setting: b[7] = 1: Enable mooth change b[6] = 0: Independent PGA Controlb[5] = 0: Disable clipping detection after digital PGAb[4:3] = 1_1: Attenuation limit of the automatic clipping suppression is -6dBb[2:1] = 01: Start automatic clipping supression after clipping is detected 40 timeb[0] = 1: Enable automatic clipping suppression */{0x06,0x42}, /* ADC1L input selectb[7] = 0: Not change signal polarityb[6] = Reservedb[5:0] = 0000_10: ADC input channel select VIN2L[SE] */{0x07,0x42}, /* ADC1R input selectb[7] = 0: Not change signal polarityb[6] = Reservedb[5:0] = 0000_10: ADC input channel select VIN2R[SE] */{0x08,0x40}, /* ADC2L input selectb[7] = 0: Not change signal polarityb[6] = Reservedb[5:0] = 0000_00: ADC input channel select none */{0x10,0x00}, /* GPIO1/2 configurationb[7] = 0: GPIO1 normal polarityb[6:4] = 000: GPIO1b[3] = 0: GPIO0 normal polarityb[2:0] = 000: GPIO0*/{0x11,0x00}, /* GPIO3/4 configurationb[7] = 0: GPIO3 normal polarityb[6:4] = 000: GPIO3b[3] = 0: GPIO4 normal polarityb[2:0] = 000: GPIO4*/{0x20,0x11}, /* SCK configurationb[7:6] = 00: SCK/Xtal select SCK or Xtalb[5] = 0: Select SCKb[4] = 1: I2S master modeb[3:1] = 000: ADC/DSP clock source select, ignored if auto clock detector enabledb[0] = 1: Enable auto clock detector *//* Page 3 Configuration */{0x00,0x03}, /* Register page selection = page 3 */{0x15,0x00}, /* Mic controlb[4] = 0: Disable mic bias resistor bypassb[0] = 0: Power down mic bias control */{0x00,0x00}, /* Register page selection = page 0 */ };

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