生活随笔
收集整理的這篇文章主要介紹了
verilog实现简单的除法运算
小編覺得挺不錯的,現(xiàn)在分享給大家,幫大家做個參考.
設(shè)計思路：
通過verilog實現(xiàn)除法有兩大類，分別是：
基于減法操作。
基于乘法操作的算法。
8bit/8bit的除法實現(xiàn)
附錄：
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2019/07/29 16:11:22
// Design Name:
// Module Name: test_div
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// testbench //
module test_div(); reg I_clk;
reg I_rst_p;
reg I_data_valid; //輸入有效信號
reg [7:0] I_data_a; //被除數(shù)
reg [7:0] I_data_b; //除數(shù)
wire O_data_valid;
wire [7:0] O_data_shang;
wire [7:0] O_data_yushu;
c u_c(.I_clk(I_clk),.I_rst_p(I_rst_p),.I_data_valid(I_data_valid),.I_data_a(I_data_a),.I_data_b(I_data_b),.O_data_valid(O_data_valid),.O_data_shang(O_data_shang),.O_data_yushu(O_data_yushu)
);
always #3.125 I_clk <= ~I_clk;
initial beginI_clk = 0;I_rst_p = 1;I_data_valid = 0;I_data_a = 0;I_data_b = 0;#10;I_rst_p = 0;#30;@(posedge I_clk ) begin I_data_valid = 1;I_data_a = {$random}%256; I_data_b = {$random}%20;endrepeat(18) @(posedge I_clk) I_data_valid = 0;@(posedge I_clk ) begin I_data_valid = 1;I_data_a = {$random}%256; I_data_b = {$random}%20;endrepeat(18) @(posedge I_clk) I_data_valid = 0;@(posedge I_clk ) begin I_data_valid = 1;I_data_a = {$random}%256; I_data_b = {$random}%20;endrepeat(10) @(posedge I_clk) I_data_valid = 0; @(posedge I_clk ) begin I_data_valid = 1;I_data_a = {$random}%256; I_data_b = {$random}%20;endrepeat(18) @(posedge I_clk) I_data_valid = 0;;
endendmodule
module c(input I_clk,input I_rst_p,input I_data_valid,input [7:0] I_data_a,input [7:0] I_data_b,output reg O_data_valid,output reg [7:0] O_data_shang,output reg [7:0] O_data_yushu);
reg [7:0] tempa;
reg [7:0] tempb;
reg [15:0] temp_a;
reg [15:0] temp_b;
reg div_start;
reg div_start_d1;
wire div_start_neg;
reg [4:0] div_cnt;
always@(posedge I_clk or posedge I_rst_p)beginif(I_rst_p)begintempa <= 8'h0; tempb <= 8'h0; endelse if(I_data_valid)begintempa <= I_data_a; tempb <= I_data_b; endelsebegintempa <= tempa; tempb <= tempb; endendalways@(posedge I_clk or posedge I_rst_p)beginif(I_rst_p)div_start <= 1'b0;else if(I_data_valid && div_start == 1'b0)div_start <= 1'b1; //開始計算else if(div_cnt == 5'd16 ) //每16個時鐘后開始下一次計算div_start <= 1'b0;elsediv_start <= div_start;end
//========================================================div_cnt 計數(shù)器
always@(posedge I_clk or posedge I_rst_p)if(I_rst_p)div_cnt <= 5'd0;else if(div_start)div_cnt <= div_cnt + 1;elsediv_cnt <= 5'd0;
//=======================================================
always@(posedge I_clk or posedge I_rst_p)beginif(I_rst_p)begintemp_a <= 16'h0;temp_b <= 16'h0; endelse if(div_start )if(div_cnt == 4'd0)begintemp_a <= {8'h0,tempa};temp_b <= {tempb,8'h0};endelse if(div_cnt[0] == 1'b1)begintemp_a <= {temp_a[14:0],1'b0}; //相當(dāng)于乘2 或者左移一位elsebegintemp_a <= (temp_a[15:8] >= temp_b[15:8])?(temp_a - temp_b + 1):temp_a;//判斷temp_a乘2之后取高8位與輸入的除數(shù)比較大小 , 8次移動完temp_a[15:8]<temp_b[15:8])//結(jié)果就是左邊高temp_a[15:8]是余數(shù)，右邊temp_a[7:0]是商endelsebegintemp_a <= 16'h0;temp_b <= 16'h0; endend
always@(posedge I_clk)begindiv_start_d1 <= div_start; //延一拍end
assign div_start_neg = div_start_d1 & (~div_start); //產(chǎn)生一個脈沖always@(posedge I_clk or posedge I_rst_p)beginif(I_rst_p)beginO_data_valid <= 1'b0;O_data_shang <= 1'b0;O_data_yushu <= 1'b0; endelse if(div_start_neg)beginO_data_valid <= 1'b1;O_data_shang <= temp_a[7:0];O_data_yushu <= temp_a[15:8]; endelsebeginO_data_valid <= 1'b0;O_data_shang <= 1'b0;O_data_yushu <= 1'b0; endend
endmodule
仿真結(jié)果：
總結(jié)
以上是生活随笔為你收集整理的verilog实现简单的除法运算的全部內(nèi)容，希望文章能夠幫你解決所遇到的問題。
如果覺得生活随笔網(wǎng)站內(nèi)容還不錯，歡迎將生活随笔推薦給好友。
