UBOOT I2C读写详解（基于mini2440）
mini2440 UBOOT I2C支持總結
1.?mini2440開發板I2C連接的設備
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SDA/SCL對應的引腳：
??
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2.?AT24C08地址
查看AT24C08芯片手冊
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ADDRESS數據段為1010xxx（xxx為A2/A1/A0pin腳連接的電平），由于這里A2/A1/A0都為低電平，所以地址為1010000即0x50
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3.?UBOOT下12C調試命令
這里假定I2C設備的地址為0x50.
1）從0寄存器開始讀，讀16個字節：
u-boot> i2c md 0x50 0 16
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Md:12c讀命令
0x50:i2c外設的地址
0：從外設芯片的第0號寄存器開始讀
16：總共讀16個寄存器
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2）寫i2c地址為0x50的外設芯片，給偏移為1的寄存器寫0x12.
U-boot> i2c mw 0x20 01 0x12
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Mw:i2c寫
0x50:i2c外設的地址。
01：寫外設芯片偏移為1的寄存器
0x12：給寄存器寫的值為0x12.
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4.?UBOOT S3C2440 I2C code
所在文件：s3c24x0_i2c.c
/*
?* (C) Copyright 2002
?* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
?*
?* See file CREDITS for list of people who contributed to this
?* project.
?*
?* This program is free software; you can redistribute it and/or
?* modify it under the terms of the GNU General Public License as
?* published by the Free Software Foundation; either version 2 of
?* the License, or (at your option) any later version.
?*
?* This program is distributed in the hope that it will be useful,
?* but WITHOUT ANY WARRANTY; without even the implied warranty of
?* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
?* GNU General Public License for more details.
?*
?* You should have received a copy of the GNU General Public License
?* along with this program; if not, write to the Free Software
?* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
?* MA 02111-1307 USA
?*/
?
/* This code should work for both the S3C2400 and the S3C2410
?* as they seem to have the same I2C controller inside.
?* The different address mapping is handled by the s3c24xx.h files below.
?*/
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#include <common.h>
#include <asm/arch/s3c24x0_cpu.h>
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#include <asm/io.h>
#include <i2c.h>
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#ifdef CONFIG_HARD_I2C
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#define I2C_WRITE 0
#define I2C_READ 1
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#define I2C_OK 0
#define I2C_NOK 1
#define I2C_NACK 2
#define I2C_NOK_LA 3 /* Lost arbitration */
#define I2C_NOK_TOUT 4 /* time out */
?
#define I2CSTAT_BSY 0x20 /* Busy bit */
#define I2CSTAT_NACK 0x01 /* Nack bit */
#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
#define I2C_MODE_MR 0x80 /* Master Receive Mode */
#define I2C_START_STOP 0x20 /* START / STOP */
#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
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#define I2C_TIMEOUT 1 /* 1 second */
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static int GetI2CSDA(void)
{
????//獲取GPIO的基地址，然后通過偏移獲取到各個GPIO
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
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#if defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) //lwx312267-018
return (readl(&gpio->GPEDAT) & 0x8000) >> 15;
#endif
#ifdef CONFIG_S3C2400
return (readl(&gpio->PGDAT) & 0x0020) >> 5;
#endif
}
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#if 0
static void SetI2CSDA(int x)
{
rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15;
}
#endif
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static void SetI2CSCL(int x)
{
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
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#if defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) //lwx312267-018 GPE14
writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, &gpio->GPEDAT);
#endif
#ifdef CONFIG_S3C2400
writel((readl(&gpio->PGDAT) & ~0x0040) | (x & 1) << 6, &gpio->PGDAT);
#endif
}
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//超時機制，等待當前是否有發送/接收中斷掛起
static int WaitForXfer(void)
{
????//獲取I2C寄存器基地址，再通過偏移得到各個控制寄存器
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
int i;
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i = I2C_TIMEOUT * 10000;
while (!(readl(&i2c->IICCON) & I2CCON_IRPND) && (i > 0)) {
udelay(100);
i--;
}
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return (readl(&i2c->IICCON) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
}
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static int IsACK(void)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
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return !(readl(&i2c->IICSTAT) & I2CSTAT_NACK);
}
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static void ReadWriteByte(void)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
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writel(readl(&i2c->IICCON) & ~I2CCON_IRPND, &i2c->IICCON);
}
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void i2c_init(int speed, int slaveadd)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
ulong freq, pres = 16, div;
int i;
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/* wait for some time to give previous transfer a chance to finish */
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i = I2C_TIMEOUT * 1000;
while ((readl(&i2c->IICSTAT) && I2CSTAT_BSY) && (i > 0)) {
udelay(1000);
i--;
}
????//時序開始的標志是SCL為高,而SDA由高轉低
????//這里之前的傳輸還沒有結束
if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
#if defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) //lwx312267-018
ulong old_gpecon = readl(&gpio->GPECON);
#endif
#ifdef CONFIG_S3C2400
ulong old_gpecon = readl(&gpio->PGCON);
#endif
/* bus still busy probably by (most) previously interrupted
???transfer */
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#if defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) //lwx312267-018
/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000,
???????&gpio->GPECON);
#endif
#ifdef CONFIG_S3C2400
/* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
writel((readl(&gpio->PGCON) & ~0x00003c00) | 0x00001000,
???????&gpio->PGCON);
#endif
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/* toggle I2CSCL until bus idle */
SetI2CSCL(0);
udelay(1000);
i = 10;
while ((i > 0) && (GetI2CSDA() != 1)) {
SetI2CSCL(1);
udelay(1000);
SetI2CSCL(0);
udelay(1000);
i--;
}
SetI2CSCL(1);
udelay(1000);
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/* restore pin functions */
#if defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) //lwx312267-018
writel(old_gpecon, &gpio->GPECON);
#endif
#ifdef CONFIG_S3C2400
writel(old_gpecon, &gpio->PGCON);
#endif
}
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/* calculate prescaler and divisor values */
//這里查詢下IICCON bit6的注釋
freq = get_PCLK();
if ((freq / pres / (16 + 1)) > speed)
/* set prescaler to 512 */
pres = 512;
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div = 0;
while ((freq / pres / (div + 1)) > speed)
div++;
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/* set prescaler, divisor according to freq, also set
?* ACKGEN, IRQ */
writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->IICCON);
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/* init to SLAVE REVEIVE and set slaveaddr */
writel(0, &i2c->IICSTAT);
writel(slaveadd, &i2c->IICADD);
/* program Master Transmit (and implicit STOP) */
writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT);
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}
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/*
?* cmd_type is 0 for write, 1 for read.
?*
?* addr_len can take any value from 0-255, it is only limited
?* by the char, we could make it larger if needed. If it is
?* 0 we skip the address write cycle.
?*/
static
int i2c_transfer(unsigned char cmd_type,
?unsigned char chip,
?unsigned char addr[],
?unsigned char addr_len,
?unsigned char data[], unsigned short data_len)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
int i, result;
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if (data == 0 || data_len == 0) {
/*Don't support data transfer of no length or to address 0 */
printf("i2c_transfer: bad call\n");
return I2C_NOK;
}
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/* Check I2C bus idle */
i = I2C_TIMEOUT * 1000;
while ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) && (i > 0)) {
udelay(1000);
i--;
}
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if (readl(&i2c->IICSTAT) & I2CSTAT_BSY)
return I2C_NOK_TOUT;
????//IIC總線應答使能
writel(readl(&i2c->IICCON) | 0x80, &i2c->IICCON);
result = I2C_OK;
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switch (cmd_type) {
case I2C_WRITE:
if (addr && addr_len) {
//外設IIC地址
writel(chip, &i2c->IICDS);
/* send START */
writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
???????&i2c->IICSTAT);
i = 0;
//想要寫的寄存器地址
while ((i < addr_len) && (result == I2C_OK)) {
result = WaitForXfer();
writel(addr[i], &i2c->IICDS);
ReadWriteByte();
i++;
}
i = 0;
//想要寫的數據
while ((i < data_len) && (result == I2C_OK)) {
result = WaitForXfer();
writel(data[i], &i2c->IICDS);
ReadWriteByte();
i++;
}
} else {
writel(chip, &i2c->IICDS);
/* send START */
writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
???????&i2c->IICSTAT);
i = 0;
while ((i < data_len) && (result = I2C_OK)) {
result = WaitForXfer();
writel(data[i], &i2c->IICDS);
ReadWriteByte();
i++;
}
}
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if (result == I2C_OK)
result = WaitForXfer();
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/* send STOP */
//除了這兩個BIT其它值都為0，即I2C_START_STOP為0
writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
ReadWriteByte();
break;
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case I2C_READ:
if (addr && addr_len) {
writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT);
//發送設備IIC地址
writel(chip, &i2c->IICDS);
/* send START */
writel(readl(&i2c->IICSTAT) | I2C_START_STOP,
???????&i2c->IICSTAT);
result = WaitForXfer();
if (IsACK()) {
i = 0;
//發送要讀取的寄存器的地址
while ((i < addr_len) && (result == I2C_OK)) {
writel(addr[i], &i2c->IICDS);
ReadWriteByte();
result = WaitForXfer();
i++;
}
????????????????//發送設備IIC地址
writel(chip, &i2c->IICDS);
/* resend START */
writel(I2C_MODE_MR | I2C_TXRX_ENA |
???????I2C_START_STOP, &i2c->IICSTAT);
ReadWriteByte();
result = WaitForXfer();
i = 0;
//讀取數據
while ((i < data_len) && (result == I2C_OK)) {
/* disable ACK for final READ */
if (i == data_len - 1)
writel(readl(&i2c->IICCON)
???????& ~0x80, &i2c->IICCON);
ReadWriteByte();
result = WaitForXfer();
data[i] = readl(&i2c->IICDS);
i++;
}
} else {
result = I2C_NACK;
}
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} else {
writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
writel(chip, &i2c->IICDS);
/* send START */
writel(readl(&i2c->IICSTAT) | I2C_START_STOP,
???????&i2c->IICSTAT);
result = WaitForXfer();
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if (IsACK()) {
i = 0;
while ((i < data_len) && (result == I2C_OK)) {
/* disable ACK for final READ */
if (i == data_len - 1)
writel(readl(&i2c->IICCON) &
???????~0x80, &i2c->IICCON);
ReadWriteByte();
result = WaitForXfer();
data[i] = readl(&i2c->IICDS);
i++;
}
} else {
result = I2C_NACK;
}
}
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/* send STOP */
writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
ReadWriteByte();
break;
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default:
printf("i2c_transfer: bad call\n");
result = I2C_NOK;
break;
}
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return (result);
}
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int i2c_probe(uchar chip)
{
uchar buf[1];
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buf[0] = 0;
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/*
?* What is needed is to send the chip address and verify that the
?* address was <ACK>ed (i.e. there was a chip at that address which
?* drove the data line low).
?*/
return i2c_transfer(I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
}
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int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
uchar xaddr[4];
int ret;
?
if (alen > 4) {
printf("I2C read: addr len %d not supported\n", alen);
return 1;
}
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if (alen > 0) {
xaddr[0] = (addr >> 24) & 0xFF;
xaddr[1] = (addr >> 16) & 0xFF;
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
}
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
?* EEPROM chips that implement "address overflow" are ones
?* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
?* address and the extra bits end up in the "chip address"
?* bit slots. This makes a 24WC08 (1Kbyte) chip look like
?* four 256 byte chips.
?*
?* Note that we consider the length of the address field to
?* still be one byte because the extra address bits are
?* hidden in the chip address.
?*/
if (alen > 0)
chip |= ((addr >> (alen * 8)) &
?CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
if ((ret =
?????i2c_transfer(I2C_READ, chip << 1, &xaddr[4 - alen], alen,
??buffer, len)) != 0) {
printf("I2c read: failed %d\n", ret);
return 1;
}
return 0;
}
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int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
uchar xaddr[4];
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if (alen > 4) {
printf("I2C write: addr len %d not supported\n", alen);
return 1;
}
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if (alen > 0) {
xaddr[0] = (addr >> 24) & 0xFF;
xaddr[1] = (addr >> 16) & 0xFF;
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
}
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
?* EEPROM chips that implement "address overflow" are ones
?* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
?* address and the extra bits end up in the "chip address"
?* bit slots. This makes a 24WC08 (1Kbyte) chip look like
?* four 256 byte chips.
?*
?* Note that we consider the length of the address field to
?* still be one byte because the extra address bits are
?* hidden in the chip address.
?*/
if (alen > 0)
chip |= ((addr >> (alen * 8)) &
?CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
return (i2c_transfer
(I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
?len) != 0);
}
#endif /* CONFIG_HARD_I2C */
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