Verilog有限狀態機(7)

HDLBits鏈接

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前言

今天繼續更新狀態機小節的習題。

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題庫

Q3a:FSM

題目里說當s為0時，進入B狀態，然后會檢查w的值，如果在接下來的三個周期中w值恰好有兩個周期都為1，那么z輸出1，否則z輸出0。注意，由示例的波形圖看應該是不重疊檢測。

Solution

module top_module (input clk,input reset, // Synchronous resetinput s,input w,output z );parameter S0 = 1'd0, S1 = 1'd1;reg current_state, next_state;reg [1:0] counter,num_one;always @(*) begincase(current_state)S0: next_state = s ? S1 : S0;S1: next_state = S1;default:next_state = S0;endcaseendalways @(posedge clk) beginif(reset)begincurrent_state <= S0;endelse begincurrent_state <= next_state;endendalways @(posedge clk) beginif(reset)begincounter <= 2'd0;endelse if(counter == 2'd2) begincounter <= 2'd0;endelse if(current_state == S1) begincounter <= counter + 1'd1;endendalways @(posedge clk) beginif(reset) beginnum_one <= 1'd0;endelse beginif(counter == 2'd0)beginnum_one <= w ? 1'd1 : 1'd0;endelse if(current_state == S1) beginnum_one <= w ? (num_one+1'd1) : num_one;end end endassign z = (current_state == S1 && num_one == 2'd2 && counter == 2'd0);endmodule

此題中我用了兩個計數器來完成，需特別注意的是，在滿足哪種條件時計數器清零或者自加，一定注意！

Q3b:FSM

該題讓實現下圖所示的狀態機，其中復位信號讓狀態轉移至000；

Solution：

module top_module (input clk,input reset, // Synchronous resetinput x,output z );parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010;parameter S3 = 3'b011, S4 = 3'b100;reg [2:0] current_state, next_state;always @(*) begincase(current_state)S0: next_state = x ? S1 : S0;S1: next_state = x ? S4 : S1;S2: next_state = x ? S1 : S2;S3: next_state = x ? S2 : S1;S4: next_state = x ? S4 : S3;default:next_state = S0;endcaseendalways @(posedge clk) beginif(reset)begincurrent_state <= S0;endelse begincurrent_state <= next_state;endendalways @(posedge clk) beginif(reset)beginz <= 1'b0;endelse begincase(next_state)S3: z <= 1'b1;S4: z <= 1'b1;default:z <= 1'b0;endcaseend endendmodule

心得：第三段狀態機輸出用到next_state做條件時，記得要將reset條件加上，因為reset影響的是current_state，不影響next_state。

Q3c:FSM logic

由下面的狀態轉移表將Y[0]與z表示出來。

Solution：

module top_module (input clk,input [2:0] y,input x,output Y0,output z );assign Y0 = ((~y[2]&y[0])|(y==3'b100))&~x | (~y[2]&~y[0])&x;assign z = (y == 3'b011) | (y == 3'b100);endmodule

Q6b：FSM next-state logic

通過下面的狀態轉移表將Y[2]的下一狀態表示出來，其中w為輸入。

Solution：

module top_module (input [3:1] y,input w,output Y2);assign Y2 = (y == 3'b001 | y == 3'b101) & ~w | (y == 3'b001 | y == 3'b010 | y == 3'b100 | y == 3'b101) & w;endmodule

按上面我列的狀態轉移表將Y2表示出來即可。

Q6c:FSM one-hot next-state logic

這里使用了one-hot編碼，將Y2和Y4輸出出來，思路與上題類似，這里不再贅述。

Solution：

module top_module (input [6:1] y,input w,output Y2,output Y4);assign Y2 = ~w & y[1];assign Y4 = (w & y[2])|(w & y[3])|(w & y[5])|(w & y[6]);endmodule

Q6：FSM

這是個正宗的FSM題，照著圖列狀態即可。

Solution：

module top_module (input clk,input reset, // synchronous resetinput w,output z);parameter A = 3'd0, B = 3'd1, C=3'd2;parameter D = 3'd3, E = 3'd4, F=3'd5;reg [2:0] current_state, next_state;always @(*) begincase(current_state)A: next_state = w ? A : B;B: next_state = w ? D : C;C: next_state = w ? D : E;D: next_state = w ? A : F;E: next_state = w ? D : E;F: next_state = w ? D : C;default:next_state = A;endcaseendalways @(posedge clk) beginif(reset)begincurrent_state <= A;endelse begincurrent_state <= next_state;endendassign z = (current_state == E | current_state == F);endmodule

結語

今天先更新這幾題吧，FSM這部分題目都算比較基礎的題目，代碼有不足之處還望指正，狀態機部分的題終于要結束了。

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