u-boot-2020.04不支持RTL8201 PHY.

1. Patch

• https://lists.denx.de/pipermail/u-boot/2020-January/397725.html

• https://lists.denx.de/pipermail/u-boot/2020-January/397726.html

• https://elixir.bootlin.com/u-boot/v2021.04/source/drivers/net/phy/realtek.c

2. adapt

添加以下代碼到u-boot-2020.04\drivers\net\phy\realtek.c

static int rtl8201f_probe(struct phy_device *phydev) {printf("probe rtl8201f phy\n");#ifdef CONFIG_RTL8201F_PHY_RMII_TIMINGSphydev->flags |= PHY_RTL8201F_RMII_TIMINGS; #endifreturn 0; }/* RealTek RTL8201F */ static int rtl8201f_config(struct phy_device *phydev) {unsigned int reg;debug("rtl8201f config\n");if (phydev->flags & PHY_RTL8201F_RMII_TIMINGS) {phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 7);reg = phy_read(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR);reg &= ~(RMSR_RX_TIMING_MASK | RMSR_TX_TIMING_MASK);/* Set the needed Rx/Tx Timings for proper PHY operation */reg |= (RMSR_RX_TIMING_VAL << RMSR_RX_TIMING_SHIFT)| (RMSR_TX_TIMING_VAL << RMSR_TX_TIMING_SHIFT);phy_write(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR, reg);phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0);}phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 7);reg = phy_read(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR); #ifdef CONFIG_RMII_CLK_INPUT_MODEprintf("RMII clk is input mode\n");reg |= RMII_CLK_DIR_BIT; // txc input mode #elseprintf("RMII clk is output mode\n");reg &= ~(RMII_CLK_DIR_BIT); // txc output mode #endifreg |= (RMII_MODE_BIT); //RMII modephy_write(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR, reg);phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0);genphy_config_aneg(phydev);return 0; }/* Support for RTL8201F PHY */ static struct phy_driver RTL8201F_driver = {.name = "RealTek RTL8201F 10/100Mbps Ethernet",.uid = 0x1cc816,.mask = 0xffffff,.features = PHY_BASIC_FEATURES,.probe = &rtl8201f_probe,.config = &rtl8201f_config,.startup = &rtl8211e_startup,.shutdown = &genphy_shutdown, };int phy_realtek_init(void) { ......phy_register(&RTL8211F_driver);phy_register(&RTL8201F_driver);return 0; }

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