SystemVerilog例子---traffic light module traffic_light(output logic green_light,yellow_light,red_light,input sensor,input [15:0] green_downcnt,input [15:0] yellow_downcnt,input clock,input resetN); parameter R_BIT = 0,G_BIT = 1,Y_BIT = 2;enum logic [2:0] {RED = 3'd001<<R_BIT,GREEN = 3'b001<<G_BIT,YELLOW = 3'b001<<Y_BIT} State, Next;@(posedge clock, negedge resetN)if(!resetN) State <= RED;else State <= Next;always_comb begin: set_next_stateNext = State;unique case(1'b1)State[R_BIT]: if(sensor) Next = GREEN;State[G_BIT]: if(green_downcnt == 0) Next = YELLOW;State[Y_BIT]: if(yellow_downcnt == 0) Next = RED;endcase end: set_next_statealways_comb begin: set_output{green_light, yellow_light, red_light} = 3'b000;unique case(1'b1)State[R_BIT]: red_light = 1'b1;

State[G_BIT]: green_light = 1'b1;State[Y_BIT]: yellow_light = 1'b1;endcase end: set_outputendmodule

　　

posted on 2012-06-11 17:01?Neddy11 閱讀(...) 評(píng)論(...) 編輯 收藏

轉(zhuǎn)載于:https://www.cnblogs.com/Neddy/archive/2012/06/11/2545314.html

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