HLS pragmas(1)bind_storage
問題描述:在Vivado生成bit流文件時,編譯出現問題。
Resource utilization:LUT as Distributed RAM over-utilized in Top Level Design
問題解決:可以嘗試使用URAM來解決BRAM不夠用的問題,從而解決LUT資源的緊張(LUT as Distributed RAM)
從Vivado的報告可知,對URAM的利用率為零,那么如何充分利用URAM呢
Arrays on the Interface
在Vivado IP flowVitis HLS中,默認情況下將數組合成為內存元素。當使用數組作為頂級函數的參數時,Vitis HLS假定以下情況之一
1.Memory is off-chip
2.Memory is standard block RAM with a latency of 1
To configure how Vitis HLS creates these ports:
? Specify the interface as a RAM or FIFO interface using the INTERFACE pragma or directive.
? Specify the RAM as a single or dual-port RAM using the storage_typeoption of theINTERFACE pragma or directive.
? Specify the RAM latency using the latencyoption of the INTERFACE pragma or directive.
? Use array optimizationdirectives, ARRAY_PARTITION, or ARRAY_RESHAPE, to reconfigurethe structure of the array and therefore, the number of I/O ports.
Array Interface
如果沒有明確storage_type,Vitis HLS使用:
- A single-port RAM by default
- A dual-port RAM if it reduces the initation interval or reduces
latency
pragma HLS bind_storage
描述:
BIND_STORAGE pragma將代碼中的變量(數組或函數參數)賦給RTL中的特定內存類型(type)。
這種用法對于頂級函數接口上的數組很重要,因為與數組關聯的內存類型決定了在theRTL中需要的端口的數量和類型,如接口上的數組所討論的
語法:
Example
#pragma HLS bind_storage variable=coeffs type=RAM_1P impl=bramthe coeffs[128] variable is an argument to the top-level functionfoo_top. The pragma specifies that coeffs uses a single port RAM implemented on a BRAM
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